1. Field of the Invention
The present invention relates to a driving method and a driving device of a plasma display panel (PDP) and a plasma display device. More specifically, the present invention relates to an address driving circuit for applying address voltages.
2. Background Description
A PDP is a flat display that uses plasma generated via a gas discharge process to display characters or images. Tens to millions of pixels may be provided thereon in a matrix format, depending on its size. PDPs are categorized into DC PDPs and AC PDPs, according to supplied driving voltage waveforms and discharge cell structures.
Since the DC PDPs have electrodes exposed in the discharge space, they allow a current to flow in the discharge space while the voltage is supplied. Therefore, resistors are required for current restriction. Since the AC PDPs have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks in the case of discharging. Accordingly, they have a longer lifespan than the DC PDPs.
FIG. 1 shows a perspective view of an AC PDP. As shown, a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed in parallel with the address electrodes 8, on the insulation layer 7 between the address electrodes 8. Phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1 and 6 have a discharge space 11 between them and are provided facing each other so that the scan electrode 4 and the sustain electrode 5 may cross the address electrodes 8. The address electrode 8 and a discharge space 11 formed at a crossing part of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.
FIG. 2 shows a PDP electrode arrangement diagram. The PDP electrode has an m×n matrix configuration. In detail, it has address electrodes A1 to Am in the column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in the row direction, alternately. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
In general, a method for driving the AC PDP includes a reset period, an address period, and a sustain period.
In the reset period, the states of the respective cells are reset in order to smoothly address the cells. In the addressing period, the cells that are turned on and the cells that are not turned on in a panel are selected. Wall charges accumulate in the cells that are turned on (i.e., the addressed cells). In the sustain period, discharge is performed in order to actually display pictures on the addressed cells.
Since a discharge space between a scan electrode and a sustain electrode and a discharge space between a surface on which an address electrode is formed and a surface on which scan and sustain electrodes are formed operate as capacitive loads (referred to hereinafter as panel capacitors), capacitance exists on the panel. Hence, reactive power for injecting charges to the capacitance is needed in addition to power for addressing in order to apply waveforms for addressing. An address driving circuit of the PDP includes a power recovery circuit for recovering the reactive power and re-using the same, such as that disclosed in the power recovery circuit by L. F. Weber in U.S. Pat. Nos. 4,866,349 and 5,081,400.
A conventional power recovery circuit can restrict the power consumption within a predetermined level when the images which need the high power consumption are displayed. However, the conventional power recovery circuit is operated even though the images which need the low power consumption are displayed. As a result, when the images which need the low power consumption are displayed, the power consumption of the conventional power recovery circuit is higher than the circuit not having a power recovery function. For example, in the display pattern in which all discharge cells are on, the addressing voltage is continuously applied to the address electrodes. Therefore, there is no need for the power recovery operation to be performed in this display pattern. However, the power consumption increases since the conventional power recovery circuit performs the power recovery operation in this display pattern.
In addition, conventional power recovery circuits may fail to change the voltage of the panel capacitor to the desired voltage because of a switching loss of transistors or parasitic components of the circuit. The switch performs hard switching, and hence the power consumption increases.
Furthermore, the manufacturing cost of the conventional power recovery circuit is higher, since it needs four switches and two diodes. That is, the conventional power recovery circuit needs a first switch for generating the resonance current for increasing the voltage of the panel capacitor, a second switch for generating the resonance current for reducing the voltage of the panel capacitor, a third switch for supplying the addressing voltage to the panel capacitor, a fourth switch for supplying the grounding voltage to the panel capacitor, a first diode for forming the resonance path with the first switch, and a second diode for forming the resonance path with the second switch.